(1) Field of the Invention
The present invetnion relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for fabricating Dynamic Random Access Memory (DRAM) cells using selective silicon epitaxial growth over an insulating layer on the cell (device) areas. The method is particulary useful for reducing capacitor leakage currents and soft error due to Alpha particles on DRAM cells.
(2) Description of the Prior Art
Advances in the semiconductor process technologies have dramatically decreased the demiconductor device feature sizes and increased the circuit density on the integrated circuits on chips. One device type that has experienced a rapid increase in density is the array of memory cells on DRAM devices. Each memory cell consists of a single pass transistor (FET) and a storage capacitor. As the cell area decreases and the capacitance of the storage capacitor decreases, it becomes increasingly difficult to maintain sufficient charge on the capacitor due to the capacitor leakage current, and the refresh cycle time needed to maintain the charge on the capacitor becomes unacceptably short. Another problem is the natural presence of Alpha particles, which can generate electron-hole pairs resulting in soft errors in the more conventional DRAM capacitors in which their node contacts are made directly to the diffused junctions in the silicon substrate.
One method of reducing the leakage current and reducing soft error is to use a silicon-on-insulator (SOI). However, SOI technology is still too expensive and complicated for manufacturing. However, as devices are further diminished in size, the junction depths and well depths decrease proportionally. The use of a thin silicon epitaxial layer is required for future device generations to achieve these shallow device structures.
Several methods for making and using SOI have been described in the literature. For example, in U.S. Pat. No. 5,691,776 to Hebert et al. a method is described for forming field oxide regions by etching trenches in which a conformal silicon nitride (Si.sub.3 N.sub.4) is deposited over the trenches. An opening is etched in the Si.sub.3 N.sub.4 layer and a selective epitaxial growth (SEG) is used to partially fill the trenches. The SEG is then thermally oxidized to form the field oxide. In U.S. Pat. No. 5,686,343 to Lee, Lee isolates a semiconductor layer on an insulator by first forming an insulating layer on a silicon substrate, etching a window to the substrate, depositing an amorphous silicon layer that is annealed to form an epitaxial layer over the window. The epitaxial layer is patterned and a Si.sub.3 N.sub.4 layer is deposited over the patterned epitaxial layer, and a thermal oxidation is used to oxidize the silicon in the window under the semiconductor layer. In U.S. Pat. No. 6,037,199 to Huang et al. an insulating layer is formed on a silicon substrate, an opening is formed in the insulator, and an amorphous silicon layer is deposited and annealed to form an epitaxial layer extending from the opening laterally over the insulating layer. The epitaxial layer is patterned over the insulating layer to form isolated silicon regions (islands) in which FETs are forme. In. U.S. Pat. No. 5,763,314 to Chittipeddi a method is described for forming two separate selective epitaxial layers, having different dopant concentrations, on the same silicon substrate. The epitaxial layers are separated by a trench filled with an insulating material.
However, there is still a strong need in the semiconductor industry to provide DRAM cells with low capacitor-leakage currents and reduced Alpha soft errors while providing a process that is integratable into the current manufacturing process without significantly increasing manufacturing process complexity.